1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device which has an insulating film with a high aspect ratio, and which prevents a void from being formed in the insulating film.
2. Description of the Related Art
A related manufacturing method of semiconductor device is described with reference to FIG. 3 to FIG. 5. First, as shown in FIG. 3A, a pad oxide film 202 having a thickness of 9 nm is formed on a silicon semiconductor substrate 201 by thermal oxidation, and then, a silicon nitride film 203 having a thickness of 120 nm is formed on the pad oxide film 202 by an LP-CVD method. A pattern of photoresist 204 is formed on the silicon nitride film 203 by using a known lithography technique.
Next, as shown in FIG. 3B, the silicon nitride film 203 and the pad oxide film 202 are patterned by using the photoresist 204 as a mask and by a known etching technique. Then, the photoresist 204 is removed by ashing or the like in an oxygen plasma atmosphere.
Thereafter, as shown in FIG. 3C, the semiconductor substrate 201 is etched by using the patterned silicon nitride film 203 as a mask to form a hole for an isolation having a depth of 180 nm. The height of the silicon nitride film 203 is reduced to 80 nm from the height of 120 nm before the etching during etching the semiconductor substrate 201.
Next, in order to remove a damaged layer by the etching, a thermally oxidized film 205 having a thickness of about 10 nm is formed on the inner wall of the trench. Next, as shown in FIG. 4A, a silicon oxide film 206 is deposited on the whole surface by using a bias CVD method (an HDP-CVD method; High Density Plasma-Chemical Vapor Deposition Method).
Thereafter, as shown in FIG. 4B, by using the silicon nitride film 203 as a stopper, the silicon oxide film 206 is polished by a CMP using ceria slurry, to the upper end of the silicon nitride film 203, so as to be flattened. That is, in the above described related art, the nitride film 203 serves as a hard mask during trench processing (etching) of the silicon oxide film 206, and serves as a stopper during polishing the silicon oxide film 206 by the CMP.
Further, as shown in FIG. 4C, the silicon oxide film 206 is etched back by hydrofluoric acid, so that the upper end of the silicon oxide film 206 is lowered to near the lower end of silicon nitride film 203. At this time, the upper end of the silicon oxide film 206 is set at a position from 20 nm to 40 nm above the semiconductor substrate 201. This is because when the pad oxide film is removed to form a gate oxide film in a subsequent step, the silicon oxide film 206 is etched, and hence the amount of the silicon oxide film 206 as considered to be etched needs to be additionally left in advance. Therefore, the etch-back amount is determined by the thickness of the silicon oxide film 206 which is etched in the processes shown in FIG. 5A and FIG. 5B, and by the thickness of the silicon nitride film 203 at the stage of FIG. 4C.
Subsequently, as shown in FIG. 5A, the silicon nitride film 203 is selectively etched by hot phosphoric acid so as to be removed. Further, after the necessary impurity ion implanting process is completed, the pad oxide film 202 is removed by hydrofluoric acid, as shown in FIG. 5B. After washing, a gate oxide film 210 is formed by thermal oxidation.
In this way, it is possible to align the element forming surface of the substrate with the surface of the isolation region. In the above described related manufacturing method, a gate electrode (not shown) is then formed on the gate oxide film 210.
Further, Japanese Patent Laid-Open No. hei6-204332 discloses a method which is different from the above described method, and in which an isolation region is formed by such a way that after a hole is formed in a silicon substrate, the side surface of the hole is exposed, and the hole is further immersed into a solution having a predetermined composition, to fill the hole with a silicon oxide film.
In recent years, the miniaturization of devices has been advanced rapidly. According to the miniaturization of semiconductor devices, each part constituting the semiconductor devices is also required to be miniaturized. For example, as for the width between trenches constituting isolation regions, a semiconductor device having a width of 60 nm or less has been produced. In this case, the trench is embedded by the HDP-CVD method in the above described related art.
However, the HDP-CVD method for embedding the trench has approached the limit in the case of reducing the dimension of the width between the trenches to less than about 60 nm as described above. As shown in FIG. 4A, a void 207 has been caused in the trench in such case.
That is, the HDP-CVD method, which is also referred to as the bias CVD method, is a film forming method in which material molecules reach the semiconductor substrate at an angle close to the perpendicular direction during film formation, and in which the film formation and sputtering proceed at the same time. Therefore, the method is conventionally used as a film forming method suitable for embedding a predetermined material in a space (hole). However, when the space becomes narrow (for example, 80 nm or less) in comparison with the depth, the aspect ratio of the space to be embedded is increased, so as to prevent the material molecules from fully reaching the inside of the space. Further, when a phenomenon in which the sputtered material is reattached to the trench inner wall is once caused, the reattached part is closed to form a void there. The void 207 caused in this way is exposed on the surface of the semiconductor device in the subsequent process, so as to form an unintended recess in the isolation region (recess 207 in FIG. 4C and FIG. 5A).
When the void 207 is present, there has arisen a problem that in the subsequent process, an electroconductive material is embedded in the void 207, so as to cause a short circuit between adjacent gate electrodes, and thereby the manufacturing yield is lowered. Further, the occurrence of the void 207 has been unable to be completely prevented by improving the method for implementing the HDP-CVD method, such as by forming the films in multi-steps (repeating the film forming and etching steps). Further, it has been difficult to prevent the occurrence of the void by improving the hardware of the film forming apparatus.
Thus, when the related method is used, the following methods are conceivable as methods for preventing the occurrence of the void:
(a) a method of reducing the aspect ratio of the trench, and
(b) a method of reducing the depth of the hole (the height of the sum of the depth of the trench in the semiconductor substrate and the height of the silicon nitride film (mask) 203) during embedding the insulating film, by reducing the height of the silicon nitride film 203.
Thus, as for the method of (a), when the present inventors reduced the aspect ratio of the trench to be embedded, by reducing the depth of the trench to 140 nm, the insulating film was able to be embedded without the occurrence of the void, even in the case of the trench width of 50 nm. However, it was found that due to the reduction in the trench depth, isolation characteristics, such as the junction leak characteristic, are deteriorated, and that the retention time (holding time) is deteriorated in the case where the isolation region having such characteristics is used for a device such as a DRAM (Dynamic Random Access Memory). That is, the prevention of the void and the retention time are in a trade-off relation.
As for the method of (b), the present inventors reduced the film thickness of the silicon nitride film 203 from 120 nm to 80 nm, in order to reduce the depth of the trench to be embedded by the HDP-CVD method. In this case, the residual film thickness of about 40 nm of the silicon nitride film 203 was expected in the stage shown in FIG. 2B. However, when the test was actually performed, there arose a problem that in the silicon nitride film having such film thickness, the clipping was caused in the side (corner) of the silicon nitride film 203 as shown in FIG. 6, so as to make the process unstable, and hence the processing size and shape could not be formed with satisfactory reproducibility. In this way, from the viewpoint of the process stability and the processing accuracy of the semiconductor substrate, and the like, it has been difficult to perform the etching by reducing the film thickness of the silicon nitride film (mask) 203, and hence it has been necessary to provide the thick silicon nitride film (mask) 203 having a predetermined thickness.
Further, when an insulating film is formed by the above described method as disclosed in Japanese Patent Laid-Open No. hei6-204332, there is a lower limit in the thickness of the film deposited in the hole in the intermediate process, resulting in a limit in the miniaturization. Further, there is a disadvantage that the manufacturing process is complicated, resulting in become long.
As a result of an extensive investigation of the above described problems, the present inventors have reached the present invention. That is, conventionally, one layer has been used as the mask during forming the hole in the semiconductor substrate and as the polishing stopper during removing the insulating film embedded in the hole. On the other hand, in the present invention, the hard mask used during forming the hole in the semiconductor substrate and the polishing stopper used during removing the insulating film embedded in the hole are formed as separate layers, respectively, so as to thereby reduce the thickness of the polishing stopper layer. As a result, an object of the present invention is to make it possible to embed an insulating film in a hole having a high aspect ratio and a small width, without the occurrence of a void.